1. Field
One or more embodiments described herein relate to a memory device.
2. Description of the Related Art
A gate structure may be formed to include a lower conductive layer pattern having a relatively high resistance and an upper conductive layer pattern having a relatively low resistance. The gate structure may also include a contact plug to contact the upper conductive layer pattern, so that a contact resistance between the gate structure and the contact plug may be low.
However, the conductive layer patterns may be formed to have a thin thickness due to the high degree of integration required for memory devices. The conductive layer patterns may also be formed to have a contact hole for the contact plug, so as to expose only the upper conductive layer pattern. This is not easy to accomplish. Thus, electrical characteristics of memory devices may deteriorate due to a high contact resistance between the gate structure and the contact plug.